Non-volatile data storage devices, such as flash solid state drive (SSD) memory devices or removable storage cards, have allowed for increased portability of data and software applications. Flash memory devices can enhance data storage density by storing multiple bits in each flash memory cell. For example, Multi-Level Cell (MLC) flash memory devices provide increased storage density by storing 2 bits per cell, 3 bits per cell, 4 bits per cell, or more. Although increasing the number of bits per cell and reducing device feature dimensions may increase a storage density of a memory device, a bit error rate of data stored at the memory device may also increase.
Error correction coding (ECC) is often used to correct errors that occur in data read from a memory device. Prior to storage, data may be encoded by an ECC encoder to generate redundant information (e.g., “parity bits”) that are associated with parity check equations of the ECC encoding scheme and that may be stored with the data as an ECC codeword. As more parity bits are used, an error correction capacity of the ECC increases and a number of bits to store the encoded data also increases.
ECC codewords may be decoded according to variety of techniques. Some techniques may have a relatively high throughput and low power consumption but may provide relatively low error correction capability, while other techniques may provide relatively high error correction capability but may have lower throughput and increased power consumption. In order to provide high-throughput performance without sacrificing correction capability, ECC decoders may support multiple decoding modes. For example, an ECC decoder may use a low-power, high-throughput bit-flipping mode to decode received data and may transition to a higher-power, lower-throughput soft decoding mode for decoding data having an error rate that exceeds the correction capacity of the bit-flipping mode.
However, because the properties of an ECC code (also referred to as a “code”) that is used to generate the codewords may determine the number of data bits that can be independently processed in parallel, the decoding modes implemented by an ECC decoder may be constrained to have the same degree of parallelism during decoding. Design of such an ECC system may be complicated due to competing priorities with regard to silicon area and cost, power budget, error correction capability, worst-case decoding latency, and throughput requirements. For example, although a high degree of parallelism may be beneficial for throughput performance using a bit-flipping mode, the same high degree of parallelism may cause the ECC decoder to exceed a power budget using a high-resolution soft decoding mode.
As another example, a decoder may include a first set of components to support a high-resolution soft decoding mode that uses decoding messages having a first number of bits. The decoder may also include a second set of components to support a reduced-resolution soft decoding mode that uses decoding messages having a second number of bits that is less than the first number of bits. Although supporting multiple resolutions enables reduced power consumption in the reduced-resolution soft decoding mode as compared to the high-resolution soft decoding mode, including both sets of components increases a size and cost of the decoder as compared to decoders that support a single-resolution soft decoding mode.